Job Description

We are seeking a skilled and motivated Physical Design Engineer to join our dynamic team. As a Physical Design Engineer, you will play a critical role in the design and implementation of integrated circuits (ICs) or chips. You will be responsible for translating. RTL (Register Transfer Level) designs into physical layouts while meeting performance, power, and area (PPA) targets. Your expertise will contribute to the success of our cutting-edge semiconductor products.

Must-Have Skills

• Python – 1 years
• Perl – 1 years
• TCL – 1 years
• EDA (Electronic Design Automation) – 1 years

Key Responsibilities

• Collaborate with architects and RTL designers to understand design specifications and constraints.
• Implement floorplans and partitioning for complex IC designs, optimizing for PPA metrics.
• Perform detailed placement and routing of digital logic, memory, and custom blocks using industry-standard tools.
• Conduct timing closure activities, including timing analysis, optimization, and clock tree synthesis.
• Address physical design challenges such as signal integrity, power integrity, and design-for-manufacturability (DFM) issues.
• Work closely with verification and backend teams to ensure design integrity and functionality.
• Generate and review design rule checks (DRC) and layout-versus-schematic (LVS) reports to ensure compliance with foundry requirements.
• Contribute to the development and improvement of physical design methodologies and flows.
• Stay updated with the latest advancements in physical design tools, methodologies, and technologies.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field. Advanced degrees are a plus.
• Strong understanding of digital IC design fundamentals and semiconductor fabrication processes.
• Proficiency in industry-standard EDA (Electronic Design Automation) tools for physical design, such as Cadence Innovus, Synopsys ICC, or Mentor Graphics Calibre.
• Experience with scripting languages like Tcl, Perl, or Python for design automation and flow customization.
• Solid understanding of timing closure techniques, clock tree synthesis, and power optimization methodologies.
• Familiarity with place and route methodologies, floorplanning, and physical verification.
• Excellent problem-solving skills and attention to detail.
• Ability to work effectively in a team-oriented environment and communicate technical concepts clearly.
• Prior experience in ASIC or FPGA physical design is preferred but not required for recent college graduates