Responsibilities

• Development of new analog physical design architectures taking into account DfM and ESD requirements.
• Implementation of physical design based on schematic design.
• Verification of the physical design (with automated test benches).
• Tool-supported layout extraction for post-layout verification (parasitics, I/R drop, current analysis, etc.).
• Implementation of test chips (physical design).
• Cooperation and support regarding top-level integration.

Must-Have Skills

• Cadence – 10 Years

Qualifications

• A completed degree in electrical engineering, communication electronics, or a comparable qualification.
• At least 1-3 years of professional experience in the field of ‘full custom physical design’.
• Knowledge in the area of I/O interfaces, especially in the area of special requirements such as ESD in physical design.
• Fluent written and spoken English skills; German is a plus.

Skills

• Circuit design
• FinFET technology
• Package design
• Extraction and STA methodology and tools
• CAD automation methods
• Timing closure
• Synthesis
• Basic SoC Architecture and HDL languages like Verilog to be able with a logic design team for timing fixes
• DFT
• Full design cycle from RTL to GDSII

This is a general job description and the exact responsibilities and qualifications may vary based on the specific role and company.